This invention relates to phase locked loops and more particularly to optoelectronic phase locked loops with balanced photodetection for clock recovery in high-speed optical time division multiplexed systems.
High-speed optical time division multiplexing (OTDM) and wavelength division multiplexing (WDM) are key technologies to meet the bandwidth demand posed by data traffic up-surge. Clock recovery is important in OTDM receivers as it synchronizes operations such as demultiplexing and data regeneration. Single channel transmissions at rates such as 160 Gbit/s using photonic techniques for clock recovery have been achieved. These optoelectronic phase-locked loops (OE-PLL), however, include a low frequency dither signal. The dither signal, for example, may be incorporated in the loop to resolve polarity ambiguity in an error signal that arises from a DC offset proportional to average input optical power. The addition of a dither signal introduces extra system complexity and frequency modulation in the recovered clock. Although conventional oscillators and phase locked loops have been accepted, there exists a need for an OE-PLL in which the polarity ambiguity in the error signal is eliminated through balanced photodetection. Further, a need exists for a simplified system in which no dither signal is required in the loop and laser noise is cancelled through the balanced photodetection reducing timing jitter of the recovered clock. These features are particularly attractive to high-speed OTDM systems ( greater than 100 Gbit/s) when requirement on timing jitter becomes much stringent.
An aspect of the present invention provides an optoelectronic phase lock loop (OE-PLL) that includes a coupler coupled to a modulator and an attenuator. The coupler directs data to the modulator and the attenuator. Balanced photodetection is achieved by at least two serially connected photodetectors, for example, PD1 (first balanced photodetector) and PD2 (second balanced photodetector). The modulator is coupled to a first balanced photodetector. The modulator provides an error signal having a first dc offset to the first balanced photodetector. The attenuator is coupled to a second balanced photodetector and provides a second dc offset to the second balanced photodetector. The first and second balanced photodetectors provide a differential signal that corresponds to a difference of the error signal having the first dc offset and the second dc offset. The OE-PLL includes a voltage controlled oscillator (VCO) coupled to a divider and the first and second balanced photodetectors. The VCO provides a single frequency signal to the divider. The divider divides the single frequency signal into a recovered clock signal and a single frequency driving signal. The recovered clock signal is the output of the OE-PLL. Further, the single frequency driving signal is received by the modulator.
Another aspect of the present invention provides an optoelectronic phase lock loop that includes a coupler coupled to an electroabsorption (EA) modulator and a variable optical attenuator. The coupler splits a data stream to the EA modulator and the variable optical attenuator. The EA modulator is coupled to a power amplifier and a first balanced photodetector and provides an error signal having a first dc offset to the first balanced photodetector. The variable optical attenuator is coupled to a second balanced photodetector and provides a second dc offset to the second balanced photodetector. The first and second balanced photodetectors provide a differential signal to a lowpass filter that corresponds to a difference of the error signal having the first dc offset and the second dc offset. The lowpass filter is coupled to the first and second balanced photodetectors and a voltage controlled oscillator. The lowpass filter filters the differential signal and provides a correction signal to the VCO. The VCO is coupled to a power divider and provides a single frequency signal thereto having a frequency of oscillation proportional to the correction signal. The power divider is coupled to a power amplifier and splits the single frequency signal into a recovered clock signal and a single frequency driving signal. Further, the power amplifier amplifies the single frequency driving signal and provides the amplified signal to the EA modulator.